Controlling HPS EMAC from FPGA Fabric (Nios II)

I don't know of anyone who has done that yet but the HPS was designed with that use case in mind. You'll want to make sure the interrupt line for the EMAC gets routed into the FPGA since Nios II should be servicing those interrupts and not the processors in the HPS block. To access the CSRs you'll want to put an address span expander (window bridge) between the Nios II core and the FPGA-to-HPS bridge so that you only expose a subset of the 4GB address space to the Nios II data master.