Forum Discussion

Honored Contributor

8 years ago

Contraining source synchronous interfaces

Hello all! I'm trying to understand how to constrain source synchronous interfaces and I'm having some difficulties. Could someone please explain the following: When we have two fl...

Altera_Forum

Honored Contributor

8 years ago

--- Quote Start ---

Launch is always first then data is latched on next clock. Who says otherwise?

--- Quote End ---

Just wanted to bring to your attention that Altera's documentation says otherwise. Screenshot from AN433, page 4:

https://alteraforum.com/forum/attachment.php?attachmentid=14590&stc=1

Forum Discussion

Contraining source synchronous interfaces

Recent Discussions

Request for COO info

JTAG Chain Broken on Agilex 7-I Dev Kit

Feasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LP

Question

Will serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?