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Altera_Forum
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8 years ago

Contraining source synchronous interfaces

Hello all! I'm trying to understand how to constrain source synchronous interfaces and I'm having some difficulties. Could someone please explain the following: When we have two fl...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Inside fpga's rtl chain the default is strict that latch is on next edge. At io you the user have other choices. Remember the clk edge is arbitrary and what matters is sampling correctly rather specifically on a given clock edge.