Constraints in SDC file

You can figure it out from the TimeQuest create_generated_clock documentation and from the example at http://www.altera.com/support/examples/timequest/exm-tq-generated-clock.html.

Be aware of the cautions at http://www.alteraforum.com/forum/showthread.php?t=2388 if you insist on using logic to drive a clock signal. Maybe you can change your design to a better implementation like a clock enable as discussed in the other thread. If this is for a class assignment, it would be best to learn how to follow the preferred FPGA recommended design practices for clocks.