Constraints from LVDS blocks and logic

Thanks Rysc. I've tried the set_clock_uncertainty and it didn't make any difference to the output. I put a clock_uncertaintly setup on the lvds clock and the lvds enable. What I can say is that using the lvds enable (on c1 of the pll) for the logic as well, has improved it. If you consider a 64 bits bus split into 4 lanes, then we should get a 0707 pattern on each lane but instead we get the following (lane0 is bits 15 to 0, lane is bits 32 to 16 etc):

lane0: 0707

lane1: 0E07

lane2: 070E

lane3: 0E07

All timing constraints have been met - setup and hold. I also have DPA on the lvds block which might be making things worse.

I have tried all paths before and when the device gets full, it struggles to find the extra routing for the delay to meet any hold time requirements.

I noticed that there a tcl commands called 'max_clock_arrival_skew' and 'max_data_arrival_skew'. Not sure if we can use these or not? Can tcl commands as .sdc commands - are they usable in this way?

Thanks

MT