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Altera_Forum
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17 years ago

Constraints from LVDS blocks and logic

Hi, I have a lvds tx and rx blocks in a Stratix3. There a 20 bits with deserialisation factor of 4. With the Rx side, the data leaving the lvds is registered. The lvds and registers are using c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

With a 0ns hold requirement, it's almost impossible to get a hold failure without some clock skew, but since the clock may use a dedicated path to the LVDS, that's certainly possible(I don't remember off the top of my head). Two points, make sure you have derive_clock_uncertainty in your .sdc file(which makes timing more difficult to meet), and in Assignments -> Settings -> Fitter, turn the Hold Optimizations to All Paths.