Constraints from LVDS blocks and logic

Rsync - apologies for the late response. I've been stuck with other things which is why I haven't had time to look at this.

We're looking into something that is related. We have the following setup: there is a pll with outputs c0(625mhz lvds clock), c1(lvds enable) and c2(with a 156.25mhz logic clock). There is a set of registers on the output of the lvds block - a 64 bit bus. What we find is that from bit 0 to bit 63, the data seems to get more corrupted. What we're thinking is that c0, c1 and c2 are all on different clock networks which may result in skew between networks but also how Quartus handles the timing in this case. What we're trying is use c1 not only as the lvds enable but also as the logic clock to force it all on one clock network.

This test version of the design works perfectly in an Stratrix 150 but not in a Stratix340. That with identical code and constraints.