Constraints from LVDS blocks and logic

Thanks for that link. I'm par way reading your doc and it's very interesting.

The thing about when I generate the constraint on the path, rather than using the clock and it doesn't work, is that I actually create that constraint in TimingQuest by right clocking on the failing path and then setting the MC from there. So, I don't actually creat that directly in the sdc file.

I understand what you are saying about the registers on the output of the lvds only presenting new data every 4 clocks since that's the deserialisation factor. I didn't add the set-up and hold constraints as these seem to be built in to the lvds stuff. So, I'm not setting these constraints and I'm just trying to meet whatever they set.

This hold requirement which is turning out to be 0 is something that Altera have set. From what you're saying, by adding that hold cycle of 3, Altera have effectively made the hold time 0ns. So, when TimingQuest tells me that I have a hold time violation, then it's telling me the truth?

All I want to do is clock the data corrctly into those registers every 156.25MHz clock cycle. I do have any additional constraints apart from that so I'm just going with whatever altera have set the setup/hold constraints to be and I'm just trying to make sure it fits that timing. I don't want to fix it by adding a constraint that's not valid.

The only way that I found that it can be fixed(without changing timing condtraints) is by changing the relationship between the 625MHz clock to the lvds and it's 156.25 enable.

Regards

MT