Constraints from LVDS blocks and logic

Here's the link:

http://www.alteraforum.com/forum/showthread.php?t=1845&highlight=timequest

If the hold constraint doesn't work on the individual path but does on the clocks, my guess is that the one of the names in the path constraint doesn't work. You should get a message about this while reading in the .sdc file(also double-click ReportSDC to see if it's there). The messages in TimeQuest are worth looking at, as there's not a whole lot of fluff.

So based on your clocks, if co feeds the LVDS receiver and c1 feeds the capture registers in the fabrice, and if you're not phase-shifting them(i.e. they're edge aligned), then the setup requirement should be 0ns and the hold requirement should be the period of the faster clock(1.6ns). Adding a multicycle -setup 4 on the path or the clocks(both should work), will make the setup requirement be 6.4ns, but as the presentation shows, the hold requirement will follow and be 4.8ns. Adding a multicycle -hold 3 will get it back to 0ns.

So if your hold requirement is 0ns and the setup requirement is 6.4ns, that means the data can pass between the two registers anywhere between 0 and 6.4ns(and clock skew will factor into that too). From a physical standpoint, I believe the output registers of the LVDS block are clocked by the fast clock, but are enabled at the deserialization rate, i.e. they're clocked by the 625MHz, but only every 4th clock(it is a parallel load of the data coming in serially). Then you have one clock cycle of the lower clock rate to transfer the data to your registers, which is what the MCs are saying.