Constraints from LVDS blocks and logic

I've looked at the the path summary tab in TimingQuest for one of the paths that has failed: from: ...generated|wire_rx_dataout[29] to: postlvds_rx_regd1[29] and it says:

Multicycle-Setup Start 4

Multicycle-Hold Start 3

Data Arrival Time 3.759

Data Required Time 4.164

Both the launch clock and latch clock start to rise at 0.8ns.

It does appear that there is this hold time hidden in there. But I don't understand where those 3 cycles went.

If I set a hold time of 1 clock (end, not start) the timing errors disappear and in the waveform, the rising edge latch clock is at 0.8ns but the sclk launch clock is now at 7.2ns and the hold relationship is shown as -6.4ns.

I don't really understand what this is telling me. I hope you can shed some light on it.

Thanks

MT