Constraints from LVDS blocks and logic

Thanks for the info.

When I say that I want a an external PLL, a pop-up box does appear but it states the clock requirements and that you need logic registers but nothing about multi-cycle constraints. However, in the ArriaGX FPGA's, if you do the same thing, it does come up with mc constraints that you must have. Interestingly enough, it doesn't include a hold constraint here either, only a set-up one.

The clock is 156.25MHz, so, with serialisation factor of 4, we get the sclk to be 4 x 156.25 = 625MHz. The enable that the lvds block needs is 156.25MHz but with a 25:75 mark space ratio.

Now, if I shift the sclk to +180 or -180 degrees and keep everything else at 0, there is no hold timing error and you can see the the sclk has shifted relative to the register clock.

MT