Constraints from LVDS blocks and logic

Does your LVDS block have the PLL, or are you creating it outside? If embedded, I think the multicycle constraints should automatically be done in the IP(or they get added when you run derive_pll_clocks). If there outside of the PLL, then in the Megawizard when you check this option, a pop-up comes on and tells you what multicycles to add. It doesn't do exact syntax or endpoints, since some of the registers are in your logic(I think). If you want to, make a side project, copy the LVDS blocks over and have them create the PLL. Throw them into a schematic and compile, and see what MCs are run when you do derive_pll_clocks.