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Honored Contributor
Honored ContributorConstraints for inverted clocks
The task looks simple, but I don’t know which constrain to use. I have to output two signals (200 MHz clocks) from FPGA. First is an inversion of the second: Mem_ClkP <= Clk; Mem_ClkN <=...
Altera_ForumHonored Contributor
Honored ContributorYou can also try ddr outputs to generate clocks (instead of data, you output '0' then '1' for one clock, '1' and '0' for the other) and apply constraints on ddr io
