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Altera_Forum
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11 years ago

Constraints for inverted clocks

The task looks simple, but I don’t know which constrain to use. I have to output two signals (200 MHz clocks) from FPGA. First is an inversion of the second: Mem_ClkP <= Clk; Mem_ClkN <=...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I wouldnt do that. The fitter will struggle to get any phase relationship between the two as the phase will be dependent on the routing of Mem_ClkN. What you need is both to be the output of a PLL, with a specified phase relationship.