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Altera_Forum's avatar
Altera_Forum
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13 years ago

constraining push button input using TimeQuest

Dear All,

have a push-button input to one of the pins in the FPGA. This passes through 2 flip-flops to get into FPGA clock domain. How can I specify this correctly in the TimeQuest? I do not want to use set_false_path. Am I obliged to do so?

thanks

.d.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    Your input isn't constrained until you put a set_input_delay constraint on it(or set_max/min_delay). Until you've constrained it, set_false_path doesn't do anything to the design. So no, you don't have to.

    Now, there is an Unconstrained Paths report that tells you what ports don't have constraints. Your push-button would show up here, and so sometimes people put a set_false_path assignment on it just to get it off this report. It has no effect on the actual design, but can help the design process(e.g. managing which ports still need constraints).
  • Altera_Forum's avatar
    Altera_Forum
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    so how should I proceed correctly?

    setup virtual clock with veeeery long period and set_input_delay to that clock?
  • Altera_Forum's avatar
    Altera_Forum
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    Do you want a constraint? Since it's going to occur asynchronously, I don't think there's anything that would be correct, and why you have two registers, since the first could go metastable. Most people do nothing, while some add a set_false_path to it so it doesn't show up as unconstrained.

  • Altera_Forum's avatar
    Altera_Forum
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    in fact, this is what I want. not to appear as unconstrained. so I'll try to fiddle with it.

    thanks
  • Altera_Forum's avatar
    Altera_Forum
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    If I might profit from your knowledge:)

    - having two asynchronous domains, where the data are transferred using two flipflops

    - declaring the two clock groups as asynchronous

    Do you need to set false path between these synchronization registers in order to get rid of timing errors resulting from the fact, that data are driven by asynchronous clock to the clock of the register being fed?
  • Altera_Forum's avatar
    Altera_Forum
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    Yes. I would do:

    set_clock_groups -asynchronous -group {

    clk_A

    clk_B

    clk_C}

    -group {

    clk_D

    clk_E}

    -group {

    clk_F

    clk_G}

    This assignment can have as many groups as you want and as many clocks in each group, but basically cuts timing between the clocks in one group from all the clocks in another group. So in the simple case of two clocks it's just:

    set_clock_groups -asynchronous -group {clk_A} -group {clk_B}

    The syntax I have above, using \ to spread across multiple lines, makes the syntax more readable with many clocks and long clock names.

    Note that the simple one is the same as:

    set_false_path -from [get_clocks {clk_A}] -to [get_clocks {clk_B}]

    set_false_path -from [get_clocks {clk_B}] -to [get_clocks {clk_A}]

    But it's done in one line instead of two. But as the number of clocks increases, set_clock_groups becomes significantly more compact and readable than a ton of set_false_paths. I talk about this in the TimeQuest User Guide on alterawiki.com.
  • Altera_Forum's avatar
    Altera_Forum
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    thanks a lot. I've read as well your timequest document. very nice reading... >>>respect!<<< :)

  • Altera_Forum's avatar
    Altera_Forum
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    In fact, this is what I want. not to appear as unconstrained. so I'll try to fiddle with it.yes i am right .......

    Thanks a lot