Forum Discussion
Altera_Forum
Honored Contributor
13 years agoIf I might profit from your knowledge:)
- having two asynchronous domains, where the data are transferred using two flipflops - declaring the two clock groups as asynchronous Do you need to set false path between these synchronization registers in order to get rid of timing errors resulting from the fact, that data are driven by asynchronous clock to the clock of the register being fed?