Constraining PLL output clocks

Use derive_pll_clocks. It creates the generated clocks for the PLL outputs. "derive_pll_clocks -create_base_clocks" will also do the create_clock for the PLL input for you.

If you prefer to create the generated clocks yourself--for example, so that you can choose the clock names--then start with derive_pll_clocks. After you see the create_generated_clock commands it provides, you can put those into your .sdc file and change the clock names.

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So does derive_pll_clocks take care of both the input and output of the pll? Must I do anything additional to relate the source clock to the pll? Thanks for the reply.

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As I said, "derive_pll_clocks -create_base_clocks" will also do the create_clock for the PLL input for you. The -create_base_clocks argument is optional; you can do the create_clock for the PLL input yourself if you prefer.

By the way, don't use the -use_tan_name argument. It creates clock names similar to those created by the Classic Timing Analyzer. If you are using strictly TimeQuest and want to use derive_pll_clocks (which I recommend), then stick with the TimeQuest naming convention.

derive_pll_clocks will produce an "Info: Deriving PLL Clocks" message. The submessages will list the create_generated_clock commands and the optional create_clock command. As I said before, you can put these into your .sdc file instead of derive_pll_clocks if you want to use different clock names. If you don't leave derive_pll_clocks in your .sdc file, however, then be especially careful to watch for a PLL cross checking warning or to run check_timing and review the pll_cross_check result.

From the on-line help:

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derive_pll_clocks

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The following table displays information for the derive_pll_clocks Tcl command:

tcl package and version

Belongs to ::quartus::sdc_ext 1.0

syntax

derive_pll_clocks [-h | -help] [-long_help] [-create_base_clocks] [-use_tan_name]

arguments

-h | -help

Short help

-long_help

Long help with examples and possible return values

-create_base_clocks

creates base clocks on input clock ports of the design that are feeding the pll

-use_tan_name

Use net names as clock names

description

Identifies PLLs or similar resources in the design and creates

generated clocks for their output clock pins. Multiple generated

clocks may be created for each output clock pin if the PLL is using

clock switchover, one for the inclk[0] input clock pin and one for the

inclk[1] input clock pin.

by default this command does not create base clocks on input clock

ports that are driving the pll. when you use the create_base_clocks

option, derive_pll_clocks also creates the base clock on an input

clock port deriving the pll. This option does not overwrite an

existing clock.

By default the clock name is the same as the output clock pin name.

To use the net name (the same name the classic Timing Analyzer would

use), use the -use_tan_name option.

example usage

project_open top

create_timing_netlist

# Create the base clock for the input clock port driving the PLL

create_clock -period 10.0 [get_ports sysclk]

# Create the generated clocks for the PLL.

derive_pll_clocks

update_timing_netlist

# Other user actions

report_timing

delete_timing_netlist

project_close

return value

Code Name Code String Return

TCL_OK 0 INFO: Operation successful

TCL_ERROR 1 ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.

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