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Altera_Forum
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17 years ago

Constraining PLL output clocks

Hello, I was wondering how I am supposed to go about constraining the output clock(s) of a PLL. I have tried using the generated clock command but using this my design fails timing analysis. I...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Use derive_pll_clocks. It creates the generated clocks for the PLL outputs. "derive_pll_clocks -create_base_clocks" will also do the create_clock for the PLL input for you.

If you prefer to create the generated clocks yourself--for example, so that you can choose the clock names--then start with derive_pll_clocks. After you see the create_generated_clock commands it provides, you can put those into your .sdc file and change the clock names.