Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorConstraining ic delays
Hi all,
I am synthesising my project and i am having timing violations wrt to IC delays. My cell delays are under control but dont know why even after adding a proper sdc the tool is not able to meet setup. I know the tool does add additional delays to meet the hold requirements but my priority is setup and i also have switched off the "optimize all hold paths" constraint. The cell delays in a path is around 2ns while the IC delays shoots upto 5ns. I dont want to use a logic lock constraint is there any othe way to meet 200Mhz for this path even if i take a 60-40 ratio of IC- CELL delays in each path. The sdc is cross checked and i have entered my requirements properly. THANKS12 Replies
Altera_ForumDo a "report_timing -setup -npaths 2 -detail full_path -file "TQ_2worstpaths.txt" and post the output file. IC delays dominate nowadays, so the ratio you're seeing doesn't seem overly egregious, but hard to say without seeing the placement. More often than not, the values are correct and the fitter is doing a good job. You need to take off ~2ns of IC delay, which is unlikely.
Also note that just adding a LogicLock constraint usually doesn't work. The fitter already knows what is critical and is working on it, so just putting the critical hierarchy into a smaller box more often than not breaks things instead of fixes them, as it just makes things more difficult.- Altera_Forum
The fanout is also in control and the paths i am talking about is REG to REG.
