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Honored Contributor
Honored ContributorConstraining ic delays
Hi all, I am synthesising my project and i am having timing violations wrt to IC delays. My cell delays are under control but dont know why even after adding a proper sdc the tool is not able ...
Altera_ForumHonored Contributor
Honored ContributorThe fanout is also in control and the paths i am talking about is REG to REG.
