Constraining ic delays

Hi all,

I am synthesising my project and i am having timing violations wrt to IC delays. My cell delays are under control but dont know why even after adding a proper sdc the tool is not able to meet setup.

I know the tool does add additional delays to meet the hold requirements but my priority is setup and i also have switched off the "optimize all hold paths" constraint.

The cell delays in a path is around 2ns while the IC delays shoots upto 5ns.

I dont want to use a logic lock constraint is there any othe way to meet 200Mhz for this path even if i take a 60-40 ratio of IC- CELL delays in each path.

The sdc is cross checked and i have entered my requirements properly.

THANKS