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Hi Kaz, thank you so much for kind reply. will this set_clock_latency take care of the routing delay from fabric to pad and back for the derived clock?
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I notice you named your input clock as output of PLL. That is not what TimeQuest sees. your first clock input is that at pin (well before PLL) i.e. the reference clock. It is up to to the tool to work out any fpga internal delays from pin to PLL input to PLL output ...etc.
Then you send it out then in again. So you have three clocks at fpga to define (two input clocks and one output). Regarding set_clock_latency I assume it is about delays outside fpga pins.
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