Constrain SDR and DDR interface on the same interface

So physically you have DDR registers in the FPGA, and when in SDR mode you ignore the data on the falling edge register? Then that is fine.

There are two main things that go into the requirement, the setup relationship and the -max external delay. So when I said there were three things to do the same thing, let's look at them for SDR 200MHz.

1) I say the external virtual clock is shifted 2.5ns and the clock driving the FPGA is not shifted. The setup relationship will come from a launch at 2.5ns and latch at 5ns, so 2.5ns. If the external -max delay is 1ns, then another 1ns is chewed up. (So basically the data can't be 1.5ns longer than the clock in the FPGA).

2) Now let's say we don't phase-shift the external clock but phase-shift the clock coming into the FPGA by 2.5ns. The launch will be at 0ns, the latch at 2.5ns, and again we have a 2.5ns setup relationship. 1ns of that is used up externally, and we have the same requirement on the FPGA.

3) Now let's say we don't phase shift anything. The launch is at 0ns and latch is at 5ns, for a 5ns setup relationship, but our external delay has been increased to 3.5ns, once again leaving 1.5ns for the FPGA to work with.

So all three of these are the same.

You mention that you're not using -waveform on the external virtual clock or the clock coming into the FPGA? If so, the setup relationship is 5ns and hold is 0ns. Let's pretend the external delays are 0ns for a moment. This is basically edge-aligned. For the FPGA to meet timing, it would need to add 2.5ns to the data path in order to get the most slack for setup and hold analysis. For example, if it added 2.5ns, it would have 2.5ns of setup slack and 2.5ns of hold slack. So this is edge-aligned. To make it say it's center-aligned, you can do one of the three things I mentioned.