Constrain SDR and DDR interface on the same interface

This is looking good in TimeQuest :).

Another small question: I get some hold violations on the paths from the FPGA pins to the first register where I clock the data on the falling edge. These hold violations are for the SDR clock and thus can be safely ignored. I was wondering how to specify these paths as false paths but only for the SDR clock. Something like this?

set_false_path -from [get_ports {ddr_in[*]}] -fall_to sdr_ext_clk