Constrain SDR and DDR interface on the same interface

The set_input_delay basically says there is an external register driving that input port. The -add_delay option says there is another register driving that port, so they are basically mutually exclusive. (It will analyze as if SDR drives it AND DDR drives it). Note that 200MHz SDR and 100MHz DDR have data coming in that looks the same, so you would really be fine just constraining one. But for completeness, I think it will be something like so

create_clock -period 5.0 -name sdr_ext_clk -waveform {2.5 5.0} ;# Adding shift to show it's "center-aligned"

create_clock -period 10.0 -name ddr_ext_clk -waveform {2.5 7.5} ;# Adding shift to show it's "center-aligned"

set_input_delay -clock sdr_ext_clk -max 1.0 [get_ports {ddr_in[*]}]

set_input_delay -clock sdr_ext_clk -min -1.0 [get_ports {ddr_in[*]}]

set_input_delay -clock ddr_ext_clk -max 1.0 [get_ports {ddr_in[*]}] -add_delay

set_input_delay -clock ddr_ext_clk -min -1.0 [get_ports {ddr_in[*]}] -add_delay

set_input_delay -clock ddr_ext_clk -max 1.0 [get_ports {ddr_in[*]}] -clock_fall -add_delay

set_input_delay -clock ddr_ext_clk -min -1.0 [get_ports {ddr_in[*]}] -clock_fall -add_delay

That's just off the top of my head so not 100%. Some notes:

- I've seen some users have -add_delay on all I/O assignments. In the above case, I would have added it to the SDR input delay assignments. Basically, it doesn't hurt anything if you do this.

- I'm pretending the data comes in with a skew of +/-1ns

- Saying the data coming in is center-aligned can be done in multiple ways and you get the same results. For example, I could have not used the -waveform option in either clock, and instead when I put a create_clock on the clock coming into the FPGA, I could have put a -waveform {2.5# #} on that, which would say the clock coming into the FPGA has been phase shifted. If you draw out the waveforms you'll see they end up with the same relationships. Finally, I could have not used a -waveform at all, and instead increased the external delays by 2.5ns, i.e. a max of 3.5 and -min of 1.5. They should all give the same slacks, and really depends on how the user wants to describe their circuit. (Personally, I think shifting the clock coming into the FPGA makes the most sense, since that's how the external device center-aligns the clock, it shifts it before sending it to the FPGA. The reason I don't always do that is now any internal paths fed by that clock have that shift. So if it's a 10ns clock, then when looking at an internal path it will have a launch edge at 2.5ns and latch at 12.5ns. The shift gets cancelled out and has no effect on slack, but can be confusing if you're not watching out for it.)