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DominiqueM's avatar
DominiqueM
Icon for New Contributor rankNew Contributor
5 years ago

Constrain DQS to memory clock for DDR memory

Hi, I am building a DDR controller on a Cyclone 10 LP device. Using various guides I have managed to constrain the DQ signals to the DQS clock for write operations. However now I am trying to figur...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Thanks.

Best regards,

KhaiY