constaint timing and ouput

I think the words "maximum" and "minimum" in the definition of output delay are quite confusing, or even misleading.

I use the following figure on slide 94 of Altera TimeQuest Timing Analyzer Online Training video to derive the output delay formulars:

http://www.alteraforum.com/forum/attachment.php?attachmentid=4932&stc=1&d=1319537862

(1) max output delay:

http://www.alteraforum.com/forum/attachment.php?attachmentid=4933&stc=1&d=1319537932

based on the above waveform, we have:

(B-A) - (C-A) = (D-C) - (D-B )

i.e., (B-A) - (C-A) + (D-B ) = (D-C)

(B-A) : output delay

(C-A): Board Data delay (Tdata_PCB )

(D-B ) : Board Clock Skew (Tclk2-Tclk1ext)

For ASSP.DIN to be captured by ASSP.CLK, (D-C) must >= Tsu of ASSP

Therefore, output delay - board data delay + board clock skew >= Tsu

output delay >= board data delay - board clock skew + Tsu

output delay max >= board delay (max) - board clock skew (min) + Tsu

From the above derivation, we can see:

(i) the so called "max" output delay is actually the minimum output delay we can set under the worst case (i.e., max board delay and min board clock skew) while still maintain the setup requrement. We can even set a larger value as the max output delay, just that it is a kind of over-constraint. Because by doing so, we move the data valid window further left, and Quartus will work harder to make Tco smaller.

(ii) the max output delay defined by the above formular is actually referenced to fpga.clk (delay from fpga.clk to fpga.dout). So why should we still use the virtual clock (ASSP.CLK) when specifying the max output delay?

(2) min output delay can be derived from the same waveform:

http://www.alteraforum.com/forum/attachment.php?attachmentid=4934&stc=1&d=1319539681

we have:

(A-B ) - (D-B ) = (C-D)-(C-A)

i.e., (A-B ) - (D-B ) + (C-A)= (C-D)

(A-B ) : -output_delay (NOTE : by definition, output_delay is always latch clock edge - data arrival point. So it should always be B-A in the above waveform, even if data arrives after the latch edge)

(D-B ): Board Clock Skew (Tclk2-Tclk1ext)

(C-A): Board Data delay (Tdata_PCB )

For correct operation, current data (ASSP.DIN) should not be captured by current latch edge (ASSP.CLK). Therefore (C-D) must >= Th.

-output_delay - Board clock skew + board data delay >= Th

output_delay <= board data delay - board clock skew - Th

output delay min <= board data delay (min) - board clock skew(max) - Th

Again, the same question:

(i) the so called "min" output delay is actually the maximum output delay we can set under the worst case (i.e., min board delay and max board clock skew) while still maintain the hold requrement. We can even set a smaller value, just that it is a kind of over-constraint.

(ii) the min output delay defined by the above formular is also referenced to FPGA.CLK. So do we still need use the virtual clock (ASSP.CLK) when using the above formular to specify the min output delay?

These are my personal opinions. Welcome any further discussion.