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Altera_Forum
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16 years ago

connecting be_n_to_the_ext_ssram[3:0] to IDT71V416 SRAM

Hello all,

I created using SOPC builder a NIOS II based system that includes an SRAM compatible with IDT71V416 listed in SOPC builder, for the SRAM, I added an IDT71V416 from Memories and Memory Controllers-->SRAM folder

the top level of the the NIOS II based system includes a 4 bit wide signal called "be_n_to_the_ext_ssram", and I dont know where to connect this signal, or even what this signal does, there is a vague description of it in Quartus II handbook volume 4 chapter 9 example 3, but I found it unhelpful

the SRAM IDT71V416 itself does not seem to have any 4 bit wide signal

can you help me with this problem

thanks in advance

js

the datasheet for the SRAM is here

http://www.olimex.com/dev/pdf/71v416_ds_74666.pdf

the top level NIOS II based system instantiation is here

//Example instantiation for system 'NIOSII'

NIOSII NIOSII_inst

(

.address_to_the_ext_flash (address_to_the_ext_flash),

.address_to_the_ext_ssram (address_to_the_ext_ssram),

.be_n_to_the_ext_ssram (be_n_to_the_ext_ssram),

.clk_0 (clk_0),

.data_to_and_from_the_ext_flash (data_to_and_from_the_ext_flash),

.data_to_and_from_the_ext_ssram (data_to_and_from_the_ext_ssram),

.in_port_to_the_button_pio (in_port_to_the_button_pio),

.out_port_from_the_led_pio (out_port_from_the_led_pio),

.out_port_from_the_seven_seg_pio (out_port_from_the_seven_seg_pio),

.read_n_to_the_ext_flash (read_n_to_the_ext_flash),

.read_n_to_the_ext_ssram (read_n_to_the_ext_ssram),

.reset_n (reset_n),

.select_n_to_the_ext_flash (select_n_to_the_ext_flash),

.select_n_to_the_ext_ssram (select_n_to_the_ext_ssram),

.sys_clk (sys_clk),

.write_n_to_the_ext_flash (write_n_to_the_ext_flash),

.write_n_to_the_ext_ssram (write_n_to_the_ext_ssram)

);

further information about .be_n_to_the_ext_ssram is here

<edited>

output [ 3: 0] be_n_to_the_ext_ssram;

<edited>

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    be_n_to_the_ext_ssram signals is for BHE/BHL of the SRAM device. Since the sram controller in SOPC Builder has 32 bit data width and requires two IDT71V416 devices, it has four bit be_n. You can refer to Altera DSP kit schematic which utilizes IDT71V416:

    http://www.altera.com/literature/ds/schem_p06_10217r_03_stratixii_dsp_board_sch_4_6_06.pdf

    If you have one IDT71V416 on your board, you need a custom interface for the sram such as attached(custom_memory -> sram_256Kx16bit).
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks for your prompt response, I unzipped the file sram_256Kx16bit_hw.tcl

    and tried to source it from Quartus II Version 9.0 Build 235 06/17/2009 SJ Web Edition

    it produced error message

    Error: invalid command name "set_module_property"

    as a 2nd attempt, I launched SOPC builder from within Quartus II, and launched system console, then sourced the file. the same error message appeared

    any help is greatly appreciated

    thanks

    js
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The *_hw.tcl is not for system console. It’s a custom component definition file for SOPC Builder and SOPC Builder reads the file automatically in its start-up.- Copy the *_hw.tcl to your Quartus II project directory.

    - Start Quartus II, open the project and launch SOPC Builder

    - You will see a new component “custom_memory -> sram_256Kx16bit” in your component Library list.I made the _hw.tcl file:- from SOPC Builder menu: File -> New component…

    - Add signals in Signals tab

    - Define timing parameters in Interfaces tab

    - Give names/group in Component Wizard tabIt’s not so complicated work. You can also modify the component parameters as you want by right-click -> Edit… , and I recommend it :) .

    Regards,
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    thanks

    it appeared automatically in the component library before and I didn't notice it, after regenerating the system with the new 16 SRAM interface, now the signal be_n_to_the_ext_ssram is 2 bits wide, and corresponds to BH_n and BL_n in the IDT71V416

    tommorrow I will download the design to the evaluation board

    thanks

    js
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I generated an SOPC system using the custom 16 bit SRAM controller sram_256Kx16bit_hw.tcl

    result:the SRAM address width was generated as 19 bits wide although the IDT71V416 (ISSI IS61WV25616BLL) has only 18 bits

    as seen below from the NIOSII_system module definition of the address to the external SRAM

    output [ 18: 0] address_to_the_ext_sram_256Kx16bit;

    what is the best action to take to connect the 18 bit SRAM address lines

    thanks

    js
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    because it's 16 bit memory, you should omitted A0 of FPGA.

    connect FPGA's A1 to SRAM's A0, A2 to A1, and so up.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi, i met this problem when i add in sram_256Kx16bit_hw.tcl in my project file, add place the new component into SOPC, pls advise.

    Error: sram_256Kx16bit_0: set_module_property: INTERNAL not allowed for EModuleProperty, must be in {[DESCRIPTION, NAME, VERSION, MODULE_TCL_FILE, MODULE_DIRECTORY, GROUP, AUTHOR, ICON_PATH, DISPLAY_NAME, LIBRARIES, DATASHEET_URL, TOP_LEVEL_HDL_FILE, TOP_LEVEL_HDL_MODULE, INSTANTIATE_IN_SYSTEM_MODULE, EDITABLE, VALIDATION_CALLBACK, EDITOR_CALLBACK, GENERATION_CALLBACK, ELABORATION_CALLBACK]}

    Error: .avalon_tristate_slave: setParameter: No parameter ENABLED

    Error: .avalon_tristate_slave: getParameter: No parameter ENABLED

    -Lavenderpuppy-
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I added flash and sram 256x16. In sopc project I have 2 address spaces: one for flash and one for sram but I have one space for data: 16 bits. Sram have 16 bit data bus and flash 8 bits. have can I connect flash and sram to one 16 bits bus?