Connect Cyclone II Board to Oscilloscope

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Hi every one, I have just did a PWM project with Cyclone II DE1. The Output is a LED. I want see the Waveform in Oscilloscope. How can I do that? How can I connect the LED as output to Oscilloscope to see the waveform?

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Since the LEDs are under the plastic cover/shield covering the board, they are hard to probe. I would recommend sending the PWM signal two places; one to the LED and the other to a GPIO pin that you can access with the oscilloscope.

For example, if the signal inside your design is called 'pwm', then you would send that signal to two pins, eg., in VHDL

led <= pwm;
gpio <= pwm;

Cheers,

Dave

Dear Dave, I am completely new in FPGA, and I don't know the VHDL as well, Could you please help me to change the parts as you mentioned and revise the code.

This is the code, actually I got if from this website. You can see the reaction of the board after compiling:

http://www.kiranjose.com/blog/2011/09/pwm-control-in-vhdl-using-altera-de1-cycloneii-development-doard/

I want see the waveform in oscilloscope.

Thank you in Advance for your great help.

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-- Quartus II VHDL Program

-- PWM Control

-- Author Kiran Jose

-- Web: www.kiranjose.com

library ieee;

use ieee.std_logic_1164.all;

entity pwm is

port

(

clk : in std_logic;

pwm_out : buffer std_logic

);

end entity;

architecture rtl of pwm is

begin

process (clk)

--variable to count the clock pulse

variable count : integer range 0 to 50000;

--variable to change duty cycle of the pulse

variable duty_cycle : integer range 0 to 50000;

--variable to determine whether to increse or decrese the dutycycle

variable flag : integer range 0 to 1;

begin

if (rising_edge(clk)) then

--increasing the count for each clock cycle

count:= count+1;

--setting output to logic 1 when count reach duty cycle value

--output stays at logic 1 @ duty_cycle <= count <=50000

if (count = duty_cycle) then

pwm_out <= '1';

end if;

--setting output to logic 0 when count reach 50000

--output stays at logic 0 @ 50000,0 <= count <= duty_cycle

if (count = 50000) then

pwm_out <= '0';

count:= 0;

--after each complete pulse the duty cycle varies

if(flag = 0) then

duty_cycle:= duty_cycle+50;

else

duty_cycle:= duty_cycle-50;

end if;

-- flag changes when duty_cycle reaches max and min value

if(duty_cycle = 50000) then

flag:= 1;

elsif(duty_cycle = 0) then

flag:= 0;

end if;

end if;

end if;

end process;

end rtl;

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I am completely new in FPGA, and I don't know the VHDL as well, Could you please help me to change the parts as you mentioned and revise the code.

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You won't learn if I simply revise the code for you, so instead I will give you hints.

The first thing you should learn is don't find code on the internet and just use it. Find yourself a VHDL tutorial and start working your way through it.

The code you have downloaded makes use of the VHDL buffer keyword. I have never used this keyword, and have never seen code that uses it. This keyword allows you to both read and write the port in a design. A more experienced VHDL coder would use an internal signal, and drive an output port, i.e., the buffer keyword would be changed to output.

So here are your tasks:

1. Modify the design to use an internal signal and an output port.

2. Add a gpio port to the top-level design, and drive that signal with the internal signal you created in (1). Add the pin assignment for the gpio port, and resynthesize the design. Connect your oscilloscope to the gpio pin (and a ground pin), and you will see the PWM waveform.

I would recommend you learn to use the Modelsim simulator. It allows you to simulate your VHDL and to see the waveforms from your design, without having to run it in hardware.

Cheers,

Dave