connect Altera FPGA to ADC with serial LVDS interface

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On this same subject, is there a way to interface a 12 bit resolution ADC with serial-LVDS output to an Altera FPGA? Altera FPGA SERDES, however, can only deseriallize up to 10 bits. (page 20 of http://www.altera.com/literature/ug/ug_altlvds.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=altlvds_tx megafunction)

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There are two way to resolve your question:

1. split 12-bit to two 6-bit;

2. use ddio + shift-register structrue