Forum Discussion

New Contributor

3 years ago

conflicting VCCIO settings

I am getting this error in Quartus for Agilex-I series FPGA: Error(11924): Bank '3B' has conflicting VCCIO settings Error(11928): 'fmc_a_clk1_m2c_p~pad' with I/O standard True Differential S...

Farabi

Regular Contributor

3 years ago

Hello,

Referring to this link : https://www.intel.com/content/www/us/en/docs/programmable/683301/current/differential-i-o-standards-specifications.html

The 1.2V if you set the IO as RX only. In LVDS option, need to select the implementation of RX/TX so it can use 1.5V standard.

regards,

Farabi

Forum Discussion

conflicting VCCIO settings

Recent Discussions

LTC Connector DE10-Standard FPGA

Issue with configuring EPCQ64A & Cyclone

Agilex5 A5EB013BB23BE4S BSDL

MAX 10 FPGA Programming Failure via JTAG – nSTATUS & CONFIG_DONE as No Connect

ASx4 Interface debug in MSEL=111 (JTAG mode)