Configuration via Protocol (CvP) on Stratix V Development Kit

Hello,

I'd like to know if anyone was able to apply Configuration via Protocol (CvP) to configure an FPGA core fabric on a development kit? Mine is Stratix V Development Kit DK-DEV-5SGXEA7/ES-OH. What exactly do I need to do in order to run CvP on an evaluation board?

The description of Altera Stratix V GX FPGA Development Kit and its Reference Manual refer to the three following FPGA configuration methods only, *with no CvP*.

- Over on-Board USB-Blaster II using the Quartus II Programmer in JTAG mode with the supplied micro-USB cable.

- Flash memory download for configuring the FPGA using stored images from the flash memory on either power-up or pressing the program load push button (S2).

- External USB-Blaster for configuring the FPGA using the external USB-Blaster.

I understand that the Stratix V FPGA device itself can do CvP and that on the prototype or production board, not the evaluation board of the development kit, the autonomous PCIe Hard IP Block is configured by the FPGA periphery image using a small external flash device.

However, to apply CvP on the development kit, do I need to program one of the two on-board CFI flash devices to contain the periphery image? Or do I just let it boot up with the Altera default image via FPP and CPLD loader, which set the Stratix V PCIe end device ready within the PCIe power-up timing specification, then run my own CvP custom software application to configure the FPGA core fabric? I know the Altera Quartus II and reference design for CvP feature are not available yet, but I can write my own CvP code.

Thanks.