Honored ContributorAfter configuration, can the user logic access the configuration device, EPCS64 for example, through the configuration pins? If can, how to do that? Use a IPcore or user defined logic? Thanks!
Honored ContributorTake a look at the altasmi_parallel megafunction user guide (http://www.altera.com/literature/ug/mfug_asmi.pdf).
Honored ContributorIf I store the code for Nios II in the serial configuration device, and the Nios II uses on-chip memory as instruction memory. After configuration, the instruction memory is blank, right? So Nios II can do nothing. How can I load the code in the serial configuration device into the on-chip instruction memory? Should I define user logic to do that? Thanks!
Honored ContributorSorry, I'm not a Nios user. Someone more knowledgible about Nios needs to handle that question.
Honored ContributorHonored ContributorYou can also specify a memory initalization file for the on-chip RAM or ROM in SOPC builder for the instruction memory to boot right from on-chip memory.
Honored ContributorPrompt the beginner.
Why fitter in Quartus Web Edition 7.1 cannot place altasmi_parallel Megafunction in chip EP3C25E144? Though, when I choose chip EP2C20Q240, errors do not arise. In altasmi_parallel Megafunction User Guide it is written, that Cyclone III supports this megafunction.
