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Altera_Forum
Honored Contributor
9 years ago --- Quote Start --- unfortunately i dont have jtag interface i only use as mode --- Quote End --- I guess this will be your first and last FPGA design without JTAG interface... Unfortunately the schematic pictures aren't readable due to bad quality, so we can't check the connections. In the part that's still readable it's unclear how your providing MSEL setting. It can be a lot like missing power supplies (POR not released), wrong MSEL, solder problems, wrong pinout. Complete & readable schematics may help, but not sure if we can do much for you from a distance.