New Contributor
Regular ContributorHi mtwieghr,
Sorry for the delay, but I will try to adress your questions as below:
1-Does the configuration CRC check always happen during FPGA configuration?
Yes, the CRC check is always performed during configuration.
2-Is the CRC_ERROR pin required for this CRC check to work?
No, the CRC_ERROR pin is only for externally indicating errors.
The CRC check still happens internally even if this pin is unused.
3-What content is actually checked by this CRC?
Only the FPGA configuration bitstream is checked.
Other data in flash (e.g., Nios II code) is not part of this CRC check.
You may also refer to Arria V Device Handbook as reference.
Regards,
Fakhrul
New ContributorHi Fakhrul, thanks for the response.
Based on what you said, I suppose the corrupted parts of the configuration shown in my first post must all be in the Nios, not the FPGA, since it wasn't caught by the CRC check.
I'd like to do some testing to verify that corrupting the FPGA image is caught by the CRC check. How do I know which part of the jic/flash memory corresponds to the FPGA bitstream?
Is there any recommendation for detecting corruption of the Nios code on the flash? Can this be done by the Nios bootloader?
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