Configuration CRC check (Arria V GX)

Would it be possible to at least get a response on either of these topics?

I read through AN 357, and it says the following:

There are two CRC error checks. One always during configuration and a second optional CRC error check that runs in the background in user mode. This document discusses the user mode CRC error detection feature.

I'm interested in the "during configuration" CRC check, but I'm unable to find any conclusive details on its operation. Most documentation does not clearly distinguish between these two types of CRC checks, making it impossible to tell which one it's referring to.

Here's some more specific questions I've been unable to answer by reading the documentation:

1. Does the "during configuration" CRC check happen no matter what, or does it require certain conditions to be met in the hardware or in the configuration itself?

2. Does the "during configuration" CRC check have anything to do with the CRC_ERROR pin? Does the CRC_ERROR pin function need to be enabled for this CRC check to work?

3. What content is actually checked? In our application the flash contains both the FPGA configuration and Nios II code, and we observe that the Nios II code can be modified independently of the FPGA configuration. So clearly the FPGA and Nios II code aren't covered by a single CRC. Does each have its own CRC? Or is the Nios II code not checked at all?