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"trying to program with signaltap also gives no errors though it still prompts me to program my device (again and again after programming..)"
Do you mean that you are not able to program through sof file also?
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thats the thing, i can see the programming sequence completes, quartus's console prompts "ended programming succesfully" and signaltap has a red mark telling me to program the device again, trying to start the sampling with/without a trigger option chosen changes the red mark to a yellow mark saying "jtag communication error", how can there be an error when it is beeing recognized by the programmer while pressing "find target" or using the jtag debugger successfully?
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I dont remember if i had anything else other than probing at various points. Try providing a capacitor between DCLK and gnd.
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i see, i appriciate the effort, everything in my design is connected based on the cyc III datasheet so if it asks for a capacitor im pretty sure it has one, though i will go and check as soon as i can
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Check for any reset that you may have provided to fpga . you can also connect an LED to any fpga pin and drive that to see if fpga is configured anytime
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another thing id like to add is that my design
did function on previous versions, trying to program 100% previously working back up sof's failed as well but it did used to work for several months before this problem occured
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