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Altera_Forum's avatar
Altera_Forum
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17 years ago

Conditional assignments with generics

Is it possible in VHDL to assign a signal conditionally based on the value of a generics without creating additional unwanted logic? I think the following code created logic to evaluate the...
Altera_Forum's avatar
Altera_Forum
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17 years ago

What you wrote should work OK. You shouldn't get a 2:1 mux for a conditional assignment with a condition that's a compile-time constant. You could use a conditional generate, but VHDL doesn't have an if/else version of a generate, e.g. 


GEN_TRUE: if (GENERIC_A > GENERIC_B) generate
begin
   signal_a <= signal_b;    
end generate GEN_TRUE;
GEN_FALSE: if not(GENERIC_A > GENERIC_B) generate
begin
   signal_a <= signal_c;
end generate GEN_FALSE;

So I'd probably stick with what you've got.