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Altera_Forum
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12 years ago

Concurrent writes in multi-ported memories

Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I have two nios cpu that can access the same M9K memory.

One cpu accesses it as 'tightly coupled data memory', the other as an avalon slave (the original plan was to tightly couple it to both cpu, but being able to directly read it over the PCIe is very useful for debug and post mortums).

Most of the locations are only written by one of the cpus - but often read by the other.

I use a modification of Dekker's algorithm when two values have to be modified together (modified because one of the cpu can only do a try_lock() action).

But I know I have a lurking bug because there is one location which can potentially be written by both cpu - but neither does it very often at all. Fixing is difficult because I can't spin due to real-time constraints.