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Altera_Forum
Honored Contributor
Honored ContributorConcurrent writes in multi-ported memories
Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_ForumHonored Contributor
Honored ContributorSince the M9K are synchronous it ought to be possible to add external logic to supress the write signal from one side.
It is also probable that only the bits that are written differently are undefined. It may even be true that a 0 always wins (or v.v.) - but I suspect that memory blocks may contain inverted data. We had some problems because SOPC silently ignored the request for 'old data' on 'read during write'. This was a 'Heisenbug' - a rebuild of the fpga with a minor change (anywhere) caused different board to fail.
