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the author of the paper that I have attached has come up with techniques to build memories for FPGA having more ports using these dual ported memories as building blocks. I have done the same. All the ports operate at the same frequency. So now that I can build a nW/nR memory I was thinking about handling concurrent writes to same memory location.
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Keep in mind that page 43 of that paper has the statement: "we assume that multiple writes to the same address are prevented by the system using the multi-ported memory, and that the result of
doing so is undefined"
Why try to handle concurrent writes to the same memory location, when such writes make no sense?
Can you provide a use-case of a system where two writes to the same location should be allowed (for a memory, not an I/O port)? As soon as you make the statement that a write on port A always wins, you have a priority for the multiplexing control.
Just an observation ...
Cheers,
Dave
Honored Contributor
