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Altera_Forum
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12 years ago

Concurrent writes in multi-ported memories

Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I think adding additional user logic to handle concurrent writes to the same memory location from two ports is going to affect performance. What if both sides are doing writes every clock, and what if that clock is very fast (e.g. 300+ MHz).

I've done tricks like implementing byte-enables in Xilinx memories by taking advantage of rising and falling clock edges and doing read-modify-write. But I'm unsure how to handle concurrent writes in general case by simply adding user logic.

Thanks,

Evgeni