Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Concurrent writes in multi-ported memories

Hello, Do Altera FPGA s have a mechanism to handle concurrent writes? From what I could find from the documentation if both ports try write to same to the same address in the same clock cycle, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

Dave... Yeah most FPGA s have a dual ported memory. But the author of the paper that I have attached has come up with techniques to build memories for FPGA having more ports using these dual ported memories as building blocks. I have done the same. All the ports operate at the same frequency. So now that I can build a nW/nR memory I was thinking about handling concurrent writes to same memory location.

Evgeni .. I went through the ' Xilinx - Conflict avoidance for synchronous clocking' . It says : When one port performs a write operation, the other port must not write into the same location, unless both ports write identical data. I too did not find any such restrictions in Altera documentation. I was thinking of implementing some algorithms to handle this situation on Altera fpgas.