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I think what you are saying is about the read-during-write behavior right?
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I guess that must have been what I was recalling :)
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But I was looking for conflicting writes ( what happens when more than 1 port, say in a 4W/8R memory try write to the same location in the same clock cycle).
There are algorithms for concurrent writes in a "shared memory" . But I couldn't find anything for multi-ported memories..
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An FPGA has at most dual-ported memory. If you wanted to emulate more ports, then you could, using a higher-frequency for the memory controller. If the memory only needed to be operated at one frequency, then your controller could perform two writes every clock, except for the case of a write to the same location. In that case, you would just discard the one that would have been over-written. If your ports are all at different clock frequencies, then you will need a FIFO on every port. Those FIFOs would contain the transaction type, transaction address, and for writes, transaction data.
You could probably construct a Qsys system with clock domain crossing bridges to a single memory.
Cheers,
Dave
Honored Contributor
