Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Computer vision

I'm working on a machine vision project where I have a high data rate (>100 MB/s) to process. The camera will be connected to the system using either GigE vision or CameraLink protocol, and let's assume for now that I have to do a simple Sobel edge detection on the images. I have the image processing code already in C and Matlab. I want to process these pixels in real time and I was told to try this on FPGAs

I have zero experience using FPGAs and so I would like some tips from you on how to get started with this task. Which tools do I have to use? I have access to a full version of Quartus and Matlab with Simulink. I have a DE2 education program board but we can buy a higher spec one if needed. I've seen NiosII and SOPC, and also C-to-Hardware Acceleration Compiler being mentionned several times. Is that the way to proceed for a complete newbie in HDLs, and if yes can you send me links to tutorials or working examples?

Are these tools already included in Quartus or do I need a separate license? What are the limitations of using this direct C language translation to HDL languages? And what is the preferred HDL to use?

I've also seen Mathworks' Simulink HDL coder and DSP builder also coming up in a few forums, and all these tools are just confusing me evern more. I would be very grateful for any advice on which direction to take.

Thanks

PS: Please accept my apologies if similar newbie questions have been posted before, but I couldn't get a clear answer to what I wanted by reading other posts.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    First off, it will be very useful to have some hardware knowledge before you start. Transfering matlab algorithms to FPGAs starts in matlab, by having someone experienced in FPGAs help re-design it from a hardware approach. Some simple concepts in C/MATLAB can be really difficult and expensive to implement on an FPGA when some simple architectural changes can make all the difference.

    Ive not used any C to HDL tools, but anything I have read/heard seems to point to poor performing implementations that can work, but not very or efficiently.

    As for HDL coder, I have used it. My opinion is that it is best suited to simple pipelined algorithms. Anything that needs a detailed level of control is best hand coded. Its great for arithmatic but not great for control logic. Again, others experience is that its great for architecting and prototyping a system, but not great for final implementation. What it is amazing for is modelling and verification. I have much love for simulink-modelsim co-simulation.

    The only downside is that none of these tools are free. Quartus is basically just a code compiler (compiling HDLs), and there are no translation tools. All of these have to be bought and come at considerable cost (I think an HDL coder licence is around $10k per seat!).

    So my advice is to learn up about digital hardware design as a first step. Or get someone in who is.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thank you Tricky for advice. I've started learning about digital hardware design and VHDL since your post. It's building up little by little.

    Can someone please tell me more about NIOS II? From the product literature that I've read, I understand that it is a soft microprocessor that can be implemented on Altera boards and I can use C to code things on it. Is it that simple?? What are the drawbacks of using the soft embedded microprocessor?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Thank you Tricky for advice. I've started learning about digital hardware design and VHDL since your post. It's building up little by little.

    Can someone please tell me more about NIOS II? From the product literature that I've read, I understand that it is a soft microprocessor that can be implemented on Altera boards and I can use C to code things on it. Is it that simple?? What are the drawbacks of using the soft embedded microprocessor?

    --- Quote End ---

    In some ways, it is that simple. If we ignore the complexities of designing the FPGA for the moment, and assume we've got a working design with a Nios, and working real hardware, writing code for the Nios is not largely different than any other embedded processor. Booting it up can be challenging, and it is a very modest performer, akin to other embedded CPUs, but with custom FPGA logic to do the heavy lifting, it can make a nice combo. It can't compete cost-wise or performance-wise with dedicated CPUs, but if you need an FPGA, then the Nios makes a nice companion for a variety of solutions, without needing a separate CPU chip.