Components in Verilog vs. VHDL

Thanks for your reply,

function fifo_use_eab ( use_eab : boolean ) return string is
begin
    if (use_eab = true) then
        return "ON";
    else
        return "OFF";
    end if ;
end function fifo_use_eab;

scfifo_component : scfifo
generic map
        (
        add_ram_output_register => "OFF",
        intended_device_family => "Cyclone III",
        lpm_numwords => fifo_depth,
        lpm_showahead => "ON",
        lpm_type => "scfifo",
        lpm_width => 8,
        lpm_widthu => fifo_depth_log2,
        overflow_checking => "ON",
        underflow_checking => "ON",
        use_eab => fifo_use_eab (fifo_use_memory)
        )
port map
        (
        clock => clock,
        sclr => sclr,
        wrreq => wrreq,
        aclr => aclr,
        data => data,
        rdreq => rdreq,
        usedw => usedw,
        empty => empty,
        full => full,
        q => q
        );