Components in Verilog vs. VHDL

I too have longed for such a 'ternary' statement in VHDL for a long time. Until it dawned upon me that I could write a function to achieve the effect. Here is one of my functions:

	function ternary( f , s : integer ; condition : string ; tr , fr : string )
		return string
		is
		begin
			if (condition = "EQ" ) then
				if ( f = s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "GT") then
				if ( f > s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "GTE") then
				if ( f >= s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "LT") then
				if ( f < s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "LTE") then
				if ( f <= s ) then
					return tr ;
				else
					return fr ;
				end if ;
			end if ;
			
		end function ternary ;

In your case you would use this as follows :

use_eab => ternary( FIFOUSEMEMORY , 1 , "EQ" , "ON" , "OFF") ,

May look a bit contrived, but it works!

VHDL handles 'overloading' so I wrote a few variants of the 'ternary' function to cover for other input parameters and return values.