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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Components in Verilog vs. VHDL

Hi,

here is an instance from a scfifo in verilog

scfifo the_user_to_master_fifo (

.aclr (reset),

.clock (clk),

.data (user_buffer_data),

.full (user_buffer_full),

.empty (user_buffer_empty),

.q (master_writedata),

.rdreq (read_fifo),

.wrreq (user_write_buffer)

);

defparam the_user_to_master_fifo.lpm_width = DATAWIDTH;

defparam the_user_to_master_fifo.lpm_numwords = FIFODEPTH;

defparam the_user_to_master_fifo.lpm_showahead = "ON";

defparam the_user_to_master_fifo.use_eab = (fifousememory == 1)? "on" : "off";

defparam the_user_to_master_fifo.add_ram_output_register = "OFF";

defparam the_user_to_master_fifo.underflow_checking = "OFF";

defparam the_user_to_master_fifo.overflow_checking = "OFF";

and here in VHDL:

scfifo_component : scfifo

GENERIC MAP (

add_ram_output_register => "OFF",

intended_device_family => "Cyclone III",

lpm_numwords => fifo_depth,

lpm_showahead => "ON",

lpm_type => "scfifo",

lpm_width => 8,

lpm_widthu => fifo_depth_log2,

overflow_checking => "ON",

underflow_checking => "ON",

use_eab => "on"

)

PORT MAP (

clock => clock,

sclr => sclr,

wrreq => wrreq,

aclr => aclr,

data => data,

rdreq => rdreq,

usedw => sub_wire0,

empty => sub_wire1,

full => sub_wire2,

q => sub_wire3

);

Now my question:

Can i use conditional signal assignments for "actuals" in generic maps in VHDL like

defparam the_user_to_master_fifo.use_eab = (fifousememory == 1)? "on" : "off";

in Verilog ?

I have tried

use_eab => ("0n" when (fifo_use_memory = 1) else "off")

but this doesent work.

Thanks,

Nicolas

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your reply,

    Great idea with the function. I now have written the function: 

    function fifo_use_eab ( use_eab : boolean ) return string is
begin
    if (use_eab = true) then
        return "ON";
    else
        return "OFF";
    end if ;
end function fifo_use_eab;
    Now i can use the function as "actual" in the generic map during the component instantiation in my code. 

    scfifo_component : scfifo
generic map
        (
        add_ram_output_register => "OFF",
        intended_device_family => "Cyclone III",
        lpm_numwords => fifo_depth,
        lpm_showahead => "ON",
        lpm_type => "scfifo",
        lpm_width => 8,
        lpm_widthu => fifo_depth_log2,
        overflow_checking => "ON",
        underflow_checking => "ON",
        use_eab => fifo_use_eab (fifo_use_memory)
        )
port map
        (
        clock => clock,
        sclr => sclr,
        wrreq => wrreq,
        aclr => aclr,
        data => data,
        rdreq => rdreq,
        usedw => usedw,
        empty => empty,
        full => full,
        q => q
        );
    That is quiet the thing.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I too have longed for such a 'ternary' statement in VHDL for a long time. Until it dawned upon me that I could write a function to achieve the effect. Here is one of my functions: 

    	function ternary( f , s : integer ; condition : string ; tr , fr : string )
		return string
		is
		begin
			if (condition = "EQ" ) then
				if ( f = s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "GT") then
				if ( f > s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "GTE") then
				if ( f >= s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "LT") then
				if ( f < s ) then
					return tr ;
				else
					return fr ;
				end if ;
			elsif (condition = "LTE") then
				if ( f <= s ) then
					return tr ;
				else
					return fr ;
				end if ;
			end if ;
			
		end function ternary ;

    In your case you would use this as follows : 

    
use_eab => ternary( FIFOUSEMEMORY , 1 , "EQ" , "ON" , "OFF") ,

    May look a bit contrived, but it works!

    VHDL handles 'overloading' so I wrote a few variants of the 'ternary' function to cover for other input parameters and return values.