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Altera_Forum's avatar
Altera_Forum
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17 years ago

"Component Instantiation" in VHDL

Hi,

I have a question in component instantiation in my VHDL code.

There are several components in my VHDL code. Some components share the same input and output ports.

But, it seems that I can only declare output ports once in one component although they are used in other components (?)

e.g. both AA and BB use the input port "a" and output port "b". My code is as follows:

Architecture structure of Project is

component AA is

port (a: in std_logic;

b: out std_logic

);

end component;

component BB is

port (a:in std_logic;

--b: out std_logic

):

begin

u1: AA port map (a,b);

u2: BB port map (a,b);

end structure;

In this way, I can pass the compilation. Am I correct?

Thank you!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    In the component instantiation the a and b have to be either ports or signals in the top levvel entity - you haven't declared them as signals in the architecture so I assume they must be ports in your top level entity.

    In which case you've connected the two outputs of your components together so although it might compile (synthesis would probably take exception to this) you won't get any meaningful results out of it.

    Also named port mapping is generally considered to be better practice than positional port mapping (at least in my experience - others may disagree).

    You probably mean to do something like this (the signals in the architecture could be ports on the entity instead). 

    Architecture structure of Project is
component AA is
    port (a: in std_logic;
           b: out std_logic
           );
end component;
component BB is
   port (a:in std_logic;
           --b: out std_logic
         ):
signal input_to_components : std_logic;
signal output_AA : std_logic;
signal output_BB : std_logic;
begin
     u1: AA port map (a => input_to_components, b => output_AA);
     u2: BB port map (a => input_to_components, b => output_BB);
end structure;