"Component Instantiation" in VHDL

In the component instantiation the a and b have to be either ports or signals in the top levvel entity - you haven't declared them as signals in the architecture so I assume they must be ports in your top level entity.

In which case you've connected the two outputs of your components together so although it might compile (synthesis would probably take exception to this) you won't get any meaningful results out of it.

Also named port mapping is generally considered to be better practice than positional port mapping (at least in my experience - others may disagree).

You probably mean to do something like this (the signals in the architecture could be ports on the entity instead).

Architecture structure of Project is
component AA is
    port (a: in std_logic;
           b: out std_logic
           );
end component;
component BB is
   port (a:in std_logic;
           --b: out std_logic
         ):
signal input_to_components : std_logic;
signal output_AA : std_logic;
signal output_BB : std_logic;
begin
     u1: AA port map (a => input_to_components, b => output_AA);
     u2: BB port map (a => input_to_components, b => output_BB);
end structure;